Various computing devices, including desktop computers, laptops, tablets, and mobile computing devices such as smart phones, include a number of memory subsystems for storing information. A memory subsystem may include a memory controller, a physical layer interface, the memory itself, and other components. One or more master components, such as processors, may access the memory subsystem to read or write data during various operations of the computing device.
Memory subsystems typically have a number of low power modes in which the subsystems consume less power than in normal active operation. The memory subsystems may be put into a low power mode during idle times between memory access operations—the longer the idle time, the lower the power mode may be. Power is expended to enter and exit a low power mode, and the power overhead is greater when entering a lower power mode. Thus, power is saved only if the sleep duration is longer than a certain threshold time (a break-even time), and the longer the sleep duration, the more power that is saved.
However, idle times are typically fragmented and difficult to predict because memory access requests may originate from multiple master components. This makes it more difficult for a memory controller to determine the low power mode that a memory subsystem should enter at any given time. Also, randomly occurring memory accesses expend more power than consecutive memory accesses because power is expended in initiating and/or ending each memory access. Further, the actual sleep duration for a memory subsystem may be shorter than the idle time because of a hysteresis timer that prevents a full transition to low power mode if the idle duration is too short. All of these issues increase the power consumption of the memory subsystem despite the availability of low power modes.